A ROM whose storage contents can be electrically erased and altered is known as an electrically erasable programmable ROM (EEPROM). In erasing the storage contents of an EEPRPOM, an ultraviolet ray is not necessary, and this feature is different from an EPROM. Therefore, erasing and altering data can be electrically carried out even if an EEPROM is mounted on a board of a configured system.
From this reason and from the viewpoint of easy-to-use, demands for EEPROMs are rapidly increasing for use with various control apparatuses and memory cards.
A conventional semiconductor integrated circuit, such as an 8 bit flash type EEPROM, is constructed as shown in FIG. 45.
Referring to FIG. 45, row address signals A.sub.o to A.sub.i are inputted to a row address buffer circuit 1 and amplified and shaped by the circuit 1. The amplified and shaped row address signals are then inputted to a row decoder circuit 2. Column address signals B.sub.i+1 to B.sub.j are inputted to a column address buffer circuit 3 and amplified and shaped by the circuit 3. The amplified and shaped column address signals are then inputted to a column decoder circuit 4. The row decoder circuit 2 selects only one word line WL of a memory cell array 5 having a plurality of memory cells MC. The column decoder circuit 4 selectively controls a gate 6A of a column select gate circuit 6 to select only one bit line BL of the memory cell array 5 for each I/O unit, totaling up to 8 bit lines BL. In this manner, one memory cell transistor MC for each I/O unit is selected from the memory cell array 5, totaling up to 8 memory cell transistors MC. Information of these eight selected memory cells MC is detected and amplified by each sense amplifier circuit 7. Eight outputs from eight sense amplifier circuits 7 are read via each output buffer circuit 8 at the same time, and outputted to an external circuit.
In the EEPROM shown in FIG. 45, the memory cell array 5 is constructed of eight memory cell array units (MCAU) 5A. For the purpose of simplicity, each unit 5A is shown as having four word lines WL, four bit lines BL, sixteen memory cells MC, and four reference memory cells RMC. In correspondence with the four bit lines BL, four gates 6A are shown in each column select gate circuit 6. One of the gates 6A is turned on by the column decoder circuit 4. The reference memory cell RMC is connected to the sense amplifier (SA) 7 via a reference bit line RBL having a reference gate RBT thereon.
In the EEPROM constructed as above, during each operation cycle, an NCE signal supplied to a write control circuit 10 becomes "O", and during a read cycle an NOE signal becomes "O".
Specifically, in writing 8-bit data in the EEPROM structured as above, each of eight data including "1" and "O" is supplied to an I/O unit for each of eight memory cells via a write data input pad (not shown) commonly used as an output buffer pad. In accordance with the supplied data, the write circuit 10 sets the potential of each bit line BL. Namely, the write circuit 10 applies a high potential for the data "O" and a low potential for the data "1" to the bit line BL selected by the input address signals. At this time, the word line WL selected by the input address signals is set to a high potential.
Namely, in writing the data "O", the selected word line WL and bit line BL are set to the high potential. As a result, hot electrons generated near at the drain D of a memory cell MC are injected to the floating gate FG of the memory cell MC, so that the threshold voltage of the memory cell MC shifts toward the positive side and the data "O" is memorized.
On the other hand, in writing the data "1", the bit line BL is set to the low potential. Therefore, hot electrons will not be injected to the floating gate FG and the threshold voltage of the memory cell MC will not shift, so that the data "1" is memorized.
In erasing data, an output from an erase control circuit 11 causes the erase gate EG to have a high voltage so that electrons injected in the floating gate FG are emitted out to the erase gate EG through the tunneling effect.
FIGS. 46 to 49 show a typical memory cell of such an EEPROM. FIG. 46 is a plan view showing the pattern of a memory cell, FIG. 47 is a cross sectional view taken along line 47-47 of FIG. 46, FIG. 48 is a cross sectional view taken along line 48-48 of FIG. 46, and FIG. 49 is an equivalent circuit. In FIGS. 46 to 49, reference numeral 31 represents a floating gate electrode of a first polysilicon layer, reference numeral 32 represents an erase gate electrode of a second polysilicon layer, and reference numeral 33 represents a control gate electrode of a third polysilicon layer, serving also as a word line. Reference numerals 34 and 35 represent a drain and source of an N-type diffusion region, respectively. Reference numeral 36 represent a bit line of an aluminum layer, reference numeral 37 represents a contact hole for connecting together the drain 34 and bit line 36, and reference numeral 38 represents a gate insulating film for a floating gate transistor area. Reference numeral 39 represents an erase gate insulating film formed between the floating gate electrode 31 and erase gate electrode 32, and reference numeral 40 represents an insulating film of an O--N--O structure (three layer structure of oxide film--nitride film--oxide film) formed between the floating gate electrode 31 and control gate electrode 33. Reference numeral 41 represents an insulating film of the O--N--O structure formed between the erase gate electrode 32 and control gate electrode 33, reference numeral 42 represents a gate insulating film of selecting transistor portion with the third polysilicon layer as the gate electrode, reference numeral 43 represents a field insulating film, and reference numeral 44 represents an interlayer insulating film.
The equivalent circuit of the memory cell having the structure described above is shown in FIG. 49. In FIG. 49, S represents a source, D represents a drain, FG represents a floating gate, CG represents a control gate, and EG represents an erase gate. The potential at nodes of the memory cell in various modes are tabulated in Table 1, showing the control gate potential V.sub.CC, drain potential V.sub.D, source potential V.sub.S erase gate potential V.sub.EG, and the state of the floating gate.
TABLE 1 ______________________________________ State of C.G. E.G. D S F.G. ______________________________________ Erase 0V High 0V 0V Electron Potential Emission Write High 5V High 0V Electron "0" Potential Potential Injection Write High 5V Low 0V Electron "1" Potential Potential Injection Read 5V 0V 1V 0V ______________________________________
Table 1 shows the biasing state at each node of the memory cell equivalent circuit.
As seen from Table 1, in erasing data of a memory cell MC, the control gate CG, drain D, and source S are set to O V, and the erase gate EC is set to a high potential (e.g., 12 V). In this state, electrons are emitted from the floating gate FG to the erase gate through the Fowler-Nordheim tunneling effect. In this case, current is hardly consumed.
In writing data to a memory cell MC, the control gate CG is set to a high potential, the erase gate EG is set to 5 V, and the source S is set to 0 V. Depending upon the data to be written to the memory cell MC, the drain D is set to a high potential or low potential.
In reading data from a memory cell MC, the control gate CG is set to 5 V, the erase gate EG is set to 0 V, the source S is set to 0 V, and the drain D is set to about 1 V. In this state, whether the memory cell MC turns on, i.e., whether current is caused to flow, is detected by the sense amplifier 7, and the data in the memory cell MC is read from the output butter 8.
In the following the read cycle which consumes current will be mainly discussed. First, the operation of writing the data "O" to a memory cell will be detailed.
FIG. 50 is a circuit diagram showing part of the write control circuit 10, and the column gate transistor 6 and memory cell MC shown in FIG. 45, to explain the write operation. FIG. 51 is a graph showing the relationship between a current I.sub.pp flowing through a memory cell MC and the drain voltage V.sub.DD during the write operation. LT used in FIG. 50 represents a write load transistor of the write circuit 10. The write load transistor LT and column select transistor 6A function as a resistor R which controls the write operating point during the write operation. Specifically, as shown in FIG. 51, the write operation runs on one of cross points OP1 and OP2 between the cell characteristic curve CC and the load characteristic curve LC of the resistor R.
For example, the total resistance of the write load transistor LT and column gate transistor 6A is set to 2.5 kilo-ohms. However, the resistance of the column gate transistor 6A is generally set to a small value in order to read data at a high speed. Therefore, the resistor R is mainly determined by the write load transistor LT.
If the gate voltages of the write load transistor LT and column gate transistor 6A are raised higher than an external write power source voltage V.sub.pp (=12.5 V), this voltage V.sub.pp is directly applied to the drain of the memory cell MC. The load characteristic curve in this state is LC1. At the operating point OP1 intersecting the cell characteristic curve CC and the load characteristic curve LC1, the write current I.sub.pp becomes 1.2 mA as shown in FIG. 51. If the data "O" is written in 8-bit memory cells at the same time, a write current 1.2 mA.times.8 bits=9.6 mA will flow. This write current is supplied from the external write power source V.sub.pp connected to the drain of the write load transistor LT.
Instead of raising the potential at the gates of the column gate transistor 6A and write load transistor LT higher than the write power source voltage V.sub.pp, the potential V.sub.pp itself may be applied to the gates. In this case, the drain voltage of the memory cell MC drops from V.sub.pp by the amount corresponding to the threshold value of the write load transistor LT. The load characteristic curve in this state is LC2. At the operating point OP2, a write current of 0.5 mA will flow.
As described above, a write current during the write operation can be changed by changing the operating point during the write operation.
Demands for a memory LS1 having the above-described memory cell structure are now increasing because it is easy to use. However, the system using such a memory requires not only the power sources V.sub.CC and V.sub.SS but also the write power source V.sub.pp, resulting in a complicated structure of the system.
Apart from the above, a system using batteries is known, and demands for an EEPROM operating with two power sources V.sub.CC and V.sub.SS are increasing.
FIG. 52 shows the structure of an EEPROM, or so-called flash type EEPROM using memory cells shown in FIGS. 46 to 49. In this example, this EEPROM has a one-byte structure outputting 8 bits. Memory cells 430 are disposed in a m-row, n-column matrix form. The sources of all memory cells are connected in common to a terminal SS. The control gates of a plurality of memory cells are connected to row lines WL1 to WLm which are in turn connected to a row decoder 431. The drains of a plurality of memory cells are connected to column lines DL1 to DLn which are in turn connected to common connection nodes N-1 to N-8 via column select transistors 433-1 to 433-n of an enhancement type whose gates are connected to column select lines CL1 to CLn connected to a column decoder 432. Connected between the common connection nodes N-1 to N-8 and an external high voltage power source terminal V.sub.pp to which a high voltage is applied during the write and erase operations, are write enhancement type load transistors 434-1 to 434-8 to the gates of which outputs NDin*1 to NDin*8 of write data control circuits 435-1 to 435-8 are supplied. The write data control circuits 435-1 to 435-8 are inputted with write data Din1 to Din8 from external terminals, and connected to the write power source terminals V.sub.pp.
In order to supply a high voltage during the write operation, a high voltage from the V.sub.pp terminal is supplied via a high voltage switching circuit 436 to the row decoder 431 and column decoder 432. The common source SS is connected to the output side of a source voltage control circuit 437 to which a high voltage is supplied via the V.sub.pp terminal. Connected to the common connection nodes N-1 to N-8 are sense amplifiers 438-1 to 438-8 having read load transistors. Connected to the output sides of the sense amplifiers 438-1 to 438-8 are output circuit 439-1 to 439-8 which output memory cell data in a output terminals,
The operation of the EEPROM shown in FIG. 52 will be described.
In writing data, a voltage 12 V is applied to the external high voltage power source terminal V.sub.pp. The high voltage 12 V at V.sub.pp terminal is supplied to the row decoder 431 and column decoder 432 via the switching circuit 436. The column select line and row select line selected by address signals A.sub.C and A.sub.R cause to select one memory cell for each output bit. Namely, in FIG. 52, eight memory cells are selected at the same time. The selected row line (e.g., WL1) and column select line (e.g., CL1) are applied with 12 V. In this condition, if the write data Din1 to Din8 are "O", about 9 V is applied from the write data control circuits 435-1 to 435-8 as NDin*1 to NDin*8. As a result, the load transistors 434-1 to 434-8 turn on, and about 6 V is applied to the selected column lines DL1 through a path from V.sub.pp terminal, to load transistors 434-1 to 434-8 and to column select transistors 433-1 to 433-8. On the other hand, if the write data Din1 to Din8 are "1", O V is applied as NDin*1 to NDin*8. Therefore, the load transistors 434-1 to 434-8 turn off and the drains of the selected memory cells are not applied with a voltage. The write operation is therefore not executed.
Next, in erasing data, about 12 V is applied to the common source SS from V.sub.pp terminal via the source voltage control circuit 437. Therefore, all column select lines CL1 to CLn and row lines WL1 to Wlm are set to 0 V, thereby erasing data of all memory cells in a flash manner.
In reading data, the write load transistors 434-1 to 434-8 continue to turn off, the SW outputted from the high voltage switching circuit 436 is used as V.sub.CC voltage (5 V). Data ("1" or "O") of memory cells selected by the column decoder and row decoder are sensed and amplifiers by sense amplifiers 438-1 to 438-8 and outputted via output circuits 439-1 to 439-8 from external output terminals.
As described above, an EEPROM can use a small size memory cell, and is suitable for memories of a large capacity.
Data is written in an EEPROM through impact ionization. Therefore, the drain current of 8 bit memory cells during the write operation becomes about 5 mA. Also during the erase operation, a current 2 to 3 mA flows from the source to the substrate when a high voltage is applied to the source, because the gate insulating film is thin and a leakage current generates between bands at the junction near the source. It is necessary to provide a high voltage power source having a capability of supplying a large current, as the write and erase high voltage power source V.sub.pp of an EEPROM. It becomes therefore necessary to provide two power sources V.sub.CC (5 V) and V.sub.pp (12 V). As shown in FIG. 53, such an EEPROM is provided with a V.sub.pp terminal in addition to V.sub.cc terminal and V.sub.SS terminal, and is not easy to use in system configuration. In FIG. 53, reference numeral 401 represents a package, reference numerals 402, 402, . . . represent a lead terminal, reference numerals 402a , 402a represent an exposed pin of each lead terminal 402, 402, reference numeral 403 represents a pad, reference numeral 404 represents a chip, and reference numeral 405 represents a bonding wire.